1. Field of the Invention
The present invention relates to a level shift circuit for converting a level of an input signal into another level.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing a level shift circuit for use with a semiconductor apparatus such as a flash memory. The level shift circuit converts the level of a power supply voltage (V.sub.cc) and a ground power supply voltage (GND) of an input signal into the level of a high positive voltage (PV) level or a high negative voltage (MV) level. Referring to FIG. 1, the conventional level shift circuit comprises an inverter INV 101, p-channel MOS transistors PT 101 to PT 104, and n-channel MOS transistors NT 101 to NT 104.
The drain of the p-channel MOS transistors PT 101 and the drain of the n-channel MOS transistors NT 101 are connected. The connected point is a node ND 101. The node ND 101 is connected to the gate of the p-channel MOS transistor PT 102 and the gate of the p-channel MOS transistor PT 103.
Likewise, the drain of the p-channel MOS transistor PT 102 and the drain of the n-channel MOS transistor NT 102 are connected. The connected point is a node ND 102. The node ND 102 is connected to the gate of the p-channel MOS transistor PT 101 and the gate of the p-channel MOS transistor PT 104.
The drain of the p-channel MOS transistor PT 103 and the drain of the n-channel MOS transistor NT 103 are connected. The connected point is a node ND 103. The node ND 103 is connected to the gate of the n-channel MOS transistor NT 104. Likewise, the drain of the p-channel MOS transistor PT 104 and the drain of the n-channel MOS transistor NT 104 are connected. The connected point is an output node ND.sub.OUT. The output node ND.sub.OUT is connected to the gate of the n-channel MOS transistor NT 103.
The sources of the p-channel MOS transistors PT 101 to PT 104 are connected to a power supply that supplies a high positive voltage PV (.gtoreq.V.sub.cc). The n-channel MOS transistors NT 101 and NT 102 are connected to a power supply that supplies a GND voltage. The sources of the n-channel MOS transistors NT 103 and NT 104 are connected to a power supply that supplies a high negative voltage MV (.ltoreq.GND).
The gate of the n-channel MOS transistor NT 101 is connected to an input line of an input signal IN. The gate of the n-channel MOS transistor NT 102 is connected to the input line of the input signal IN through the inverter INV 101. The inverter INV 101 is connected between the power supply that supplies the voltage V.sub.cc and the power supply that supplies the voltage GND. The output node ND.sub.OUT is connected to an output line of an output signal OUT.
The p-channel MOS transistors PT 101 to PT 104 and the n-channel MOS transistors NT 101 to NT 104 of the conventional level shift circuit are disposed in respective wells. In this case, the p-channel MOS transistors PT 101 to PT 104 are disposed in an n-type well. The n-type well is biased in a PV level. The n-channel MOS transistors NT 101 to NT 104 are disposed in a p-type well. The p-type well is biased in an MV level.
The conventional level shift circuit converts an input signal with the V.sub.cc level or the GND level into an output signal with the MV level or the PV level. Next, the operation of the level shift circuit in the case that the voltage of the input signal IN is varied from the V.sub.cc level (high level) to the GND level (low level) will be described.
In other words, when a signal with the V.sub.cc level is input as the input signal IN, the n-channel MOS transistor NT 101 is turned on. In addition, the n-channel MOS transistor NT 102 is turned off. Thus, the voltage of the node ND 101 becomes the GND level. Consequently, both the p-channel MOS transistors PT 102 and PT 103 are turned on. Since the p-channel MOS transistor PT 102 is in the on-state, the voltage of the node ND 102 rises to the PV level. The p-channel MOS transistor PT 101 is stably kept in the off-state. Thus, the voltage of the node ND 101 is stably kept in the GND level. The p-channel MOS transistors PT 102 and PT 103 are stably kept in the on-state.
Since the voltage of the node ND 102 is in the PV level, the p-channel MOS transistor PT 104 is turned off. In addition, since the p-channel MOS transistor PT 103 is in the on-state, the voltage of the node ND 103 rises to the PV level. Thus, the n-channel MOS transistor NT 104 is turned on. The voltage of the output node ND.sub.OUT lowers to the MV level.
Since the voltage of the output node ND.sub.OUT is in the MV level, the n-channel MOS transistor NT 103 is stably kept in the off-state. Thus, the voltage of the output node ND.sub.OUT is settled in the MV level. Consequently, the output node ND.sub.OUT outputs an output signal OUT with the MV level.
When the voltage of the input signal IN is varied from the V.sub.cc level to the GND level, the n-channel MOS transistor NT 102 is turned on. In addition, the n-channel MOS transistor NT 101 is turned off. Thus, the voltage of the node ND 102 becomes the GND level. The p-channel MOS transistors PT 101 and PT 104 are turned on. Since the p-channel MOS transistor PT 101 is in the on-state, the voltage of the node ND 101 rises to the PV level. Thus, the p-channel MOS transistors PT 102 and PT 103 are turned off and stably kept in the off-state.
Since the p-channel MOS transistor PT 104 is in the on-state, the voltage of the output node ND.sub.OUT rises to the PV level. Thus, the n-channel MOS transistor NT 103 is turned on. Consequently, the voltage of the node ND 103 lowers to the MV level. The n-channel MOS transistor NT 104 is stably kept in the off-state. The voltage of the output node ND.sub.OUT is settled in the PV level. Thus, the output node ND .sub.OUT outputs an output signal OUT with the PV level.
FIG. 2 is a schematic diagram showing another example of a conventional level shift circuit. Referring to FIG. 2, the level shift circuit comprises an inverter INV 201, p-channel MOS transistors PT 201 to PT 203, and n-channel MOS transistors NT 201 to NT 203.
The inverter INV 201 is connected between a power supply that supplies a voltage V.sub.cc and a power supply that supplies a voltage GND. An input terminal of the inverter INV 201 is connected to a supply line of an input signal IN. An output terminal of the inverter INV 201 is connected to the drain of the p-channel MOS transistor PT 202 and the gate of the p-channel MOS transistor PT 203 through the n-channel MOS transistor NT 201 whose gate is connected to the power supply that supplies the V.sub.cc voltage. In addition, the output terminal of the inverter INV 201 is connected to the drain of the n-channel MOS transistor NT 202 and the gate of the n-channel MOS transistor NT 203 through the p-channel MOS transistor PT 201 whose gate is connected to the power supply that supplies the GND voltage.
The threshold voltages of the n-channel MOS transistor NT 201 and the p-channel MOS transistor PT 201 are lower than the threshold voltages of the other transistors. Thus, the n-channel MOS transistor NT 201 and the p-channel MOS transistor PT 201 function as cut gates. In FIG. 2, reference codes ND 201 and ND 202 represent nodes. The node ND 201 is a connected point between the drain of the p-channel MOS transistor PT 202 and the gate of the p-channel MOS transistor PT 203. The node ND 202 is a connected point between the drain of the n-channel MOS transistor NT 202 and the gate of the n-channel MOS transistor NT 203.
The source of the p-channel MOS transistor PT 202 and the source of the p-channel MOS transistor PT 203 are connected to a power supply that supplies a high positive voltage PV (.gtoreq.V.sub.cc). The source of the n-channel MOS transistor NT 202 and the source of the n-channel MOS transistor NT 203 are connected to a power supply that supplies a high negative voltage MV (.ltoreq.GND).
The drain of the p-channel MOS transistor PT 203 and the drain of the n-channel MOS transistor NT 203 are connected. The connected point is an output node ND.sub.OUT. The output node ND.sub.OUT is connected to the gate of the p-channel MOS transistor PT 202. In addition, the output node ND.sub.OUT is connected to the gate of the n-channel MOS transistor NT 202. The output node ND.sub.OUT is connected to an output line of an output signal OUT.
In the level shift circuit, the p-channel MOS transistors PT 201 to PT 203 and the n-channel MOS transistors NT 201 to NT 203 are disposed in respective wells. In this case, the p-channel MOS transistors PT 201 to PT 203 are disposed in an n-type well. The n-type well is biased in the PV level. The n-channel MOS transistors NT 201 to NT 203 are disposed in a p-type well. The p-type well is biased in the MV level.
The conventional level shift circuit converts an input signal with the V.sub.cc level or the GND level into an output signal OUT with the PV level or the MV level. Next, the operation of the level shift circuit in the case that the voltage of the input signal IN is varied from the V.sub.cc level (high level) to the GND level (low level) will be described.
In other words, since the inverter INV 201 in the conventional level shift circuit inverts the level of the input signal IN, the input signal IN with the V.sub.cc level causes the voltage of the output terminal of the inverter INV 201 to become the GND level. The signal with the GND level is supplied to the node ND 201 through the n-channel MOS transistor NT 201. Thus, the signal with the GND level is supplied to the gate of the p-channel MOS transistor PT 203. In addition, the signal with the GND level is supplied to the node ND 202 through the p-channel MOS transistor PT 201. Thus, the signal with the GND level is supplied to the gate of the n-channel MOS transistor NT 203.
Consequently, the p-channel MOS transistor PT 203 is turned on. In addition, the n-channel MOS transistor NT 203 is turned off. Thus, the voltage of the output node ND.sub.OUT rises to the PV level. As a result, the p-channel MOS transistor PT 202 is stably kept in the off-state. The n-channel MOS transistor NT 202 is stably kept in the on-state. Thus, the voltage of the node ND 202 lowers to the MV level. Consequently, the n-channel MOS transistor NT 203 is stably kept in the off-state. Thus, the voltage of the output node ND.sub.OUT is settled in the PV level. At this point, the p-channel MOS transistor PT 201 becomes the cut-off state.
Thus, at this point, the output node ND.sub.OUT outputs an output signal OUT with the PV level.
When the voltage of the input signal IN varies from the V.sub.cc level to the GND level, the inverter INV 201 and the n-channel MOS transistor NT 201 cause the voltage of the node ND 201 to rise to V.sub.cc -V.sub.th level (where V.sub.th is the threshold voltage of the n-channel MOS transistor NT 201). In addition, the inverter INV 201 and the p-channel MOS transistor PT 201 causes the voltage of the node ND 202 to rise to the V.sub.cc level. Thus, the p-channel MOS transistor PT 203 is turned off. In addition, the n-channel MOS transistor NT 203 is turned on. Consequently, the voltage of the output node ND.sub.OUT lowers to the MV level. Thus, the p-channel MOS transistor PT 202 is stably kept in the on-state. In addition, the n-channel MOS transistor NT 202 is stably kept in the off-state. Consequently, the voltage of the node ND 201 rises to the PV level. Thus, the p-channel MOS transistor PT 203 is stably kept in the off-state. Consequently, the voltage of the output node ND.sub.OUT is settled in the MV level. At this point, the n-channel MOS transistor NT 201 becomes the cut-off state.
Thus, at this point, the output node ND.sub.OUT outputs an output signal with the MV level.
This operation applies to the case that the voltage of the input signal IN is varied from the GND level to the V.sub.cc level. In this case, the p-channel MOS transistors PT 201 to PT 203 and the n-channel MOS transistors NT 201 to NT 203 operate in the inverse manner of the above-described operation.
However, in the level shift circuit shown in FIG. 1, when the input signal IN with GND level-V.sub.cc level is converted into the output signal OUT with PV level-MV level, after the signal with GND level-V.sub.cc level is converted into the signal with GND level-PV level in a first stage, the signal with GND level-PV level is converted into the signal with MV level-PV level in a second stage. Thus, the layout area becomes large.
Since the level shift circuit shown in FIG. 2 is a one-staged level shift circuit and the number of transistors thereof is as small as six, the layout thereof is very easy. However, the level shift circuit shown in FIG. 2 requires cut-off gates (namely, the p-channel MOS transistor PT 201 and the n-channel MOS transistor NT 201). Unless the cut gates are composed of transistors with low threshold voltages, the following problem will take place.
An operational simulation for the conventional level shift circuit shown in FIG. 2 shows the following point. In the level shift circuit used in the operational simulation, transistors with normal threshold voltages were used for the p-channel MOS transistor PT 201 and n-channel MOS transistor NT 201 that compose the cut gates. In addition, since a two-staged inverter is used in the input stage, the voltage of the output signal OUT corresponding to the voltage of the input signal IN is the inverse of that of the circuit shown in FIG. 2.
FIG. 3 is a graph showing the result of the operational simulation of the conventional level shift circuit. FIG. 3 shows simulated results of transient response characteristics in the condition that the input signal IN is varies from the GND level to the V.sub.cc level and that V.sub.cc level=2.5 V, GND level=0 V, PV level=3.5 V, and MV level=-1.5 V. In the graph shown in FIG. 3, the horizontal axis is a time axis (in nsec), whereas the vertical axis is a voltage axis (in V). In addition, solid lines and white dots represent the input signal IN, whereas dashed lines and black dots represent the output signal OUT.
As shown in FIG. 3, in the conventional level shift circuit, the input signal IN with voltages of 0 V and 2.5 V is converted into the output signal with voltages of 3.5 and -1.5 V. However, when the level of the output signal OUT is inverted corresponding to the input signal IN, the transient characteristics deteriorate. In addition, it takes a relatively long time until the output signal OUT becomes stable. When such a simulation was performed with a large potential (namely, PV level=5 V and MV level=-3 V), the conventional level shift circuit did not operate.
Thus, in the conventional level shift circuit shown in FIG. 2, unless cut gates composed of transistors with low threshold voltages are used, the inverting operation of an output signal OUT cannot be performed at high speed. In addition, an output signal with a large amplitude cannot be output.
Moreover, when the conventional level shift circuit shown in FIG. 2 operates, a large through-current flows in the circuit. For example, when the voltage of the input signal IN is varied from the V.sub.cc level to the GND level and thereby the voltage of the output signal is inverted from the PV level to the MV level, although the voltage of the node ND 202 is tried to be raised from the MV level to the V.sub.cc level, since the n-channel MOS transistor NT 202 is in the on-state, a large through-current flows through the n-channel MOS transistor NT 202. The through-current prevents the voltage of the node ND 202 from smoothly varying. Thus, the inverting operation of the output signal OUT cannot be performed at high speed. When the potential between the PV level and the MV level is large, the output signal OUT can be inverted.